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FPGA Softcore Processors and IP Acquisition

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  • Softcore Processor Development Flow
    • This module introduces the concept of a soft processor in general, and of hardware design for the soft processor in particular. It presents an overview of soft processors, describing all the different kinds that are available from Xilinx, Altera, Microsemi, and Lattice and then goes into depth about the Nios II soft processor from Altera. The benefits of using soft processors to prevent obsolescence and provide flexibility are explained. The content guides you through a hardware design of the Nios II processor using Qsys, the Altera system design tool. Lastly, design of a custom instruction in the Nios II is presented, showing the versatility of the soft processor in an FPGA.
  • Writing Software for Softcore Processors
    • This module delves further into the development of soft processors, It describes the soft processor development flow in more detail, including the tools needed to develop software for the soft processor. It then introduces the Eclipse-based IDE for Nios II software development, and then shows how the output of the Qsys design is used to establish a Board Support Package (BSP) for the processor, which is necessary because the processor hardware design can be changed and the BSP software library must support any changes. Use of the BSP editor to configure the processor by programming control registers is demonstrated. Finally, the use of the custom instruction developed in Module 1 is presented, including the use of software macros to complete the implementation of the custom instruction.
  • IP Acquisition and Integration
    • Modern FPGA design is no longer centered on HDL module design as it is on acquisition and use of IP Cores. In this Module we will introduce IP cores including offerings from all the major vendors, Intel Altera, Xilinx, Microchip Microsemi, and Lattice. You will learn how to find, acquire, and use these cores.
  • Introducing ModelSim and Simulation for Verification
    • As we work on more complex FPGA designs, the challenges to create an error-free design mount exponentially. Having a good grasp of the tools needed to verify correctness of design has become more and more important. After introducing simulation in previous sessions, in this module we will examine simulation with ModelSim in more depth by working through some examples. This will show the utility of simulation for verification and debugging. This module will also describe in some detail how the simulator works and how it achieves concurrency through the use of delta delays. As a final step in the debugging process, the internal logic analyzer SignalTap II is introduced.